Kandou is redefining AI infrastructure through innovative interconnect technologies that significantly reduce power consumption while maintaining high bandwidth and ultra-low latency. Our mission is to make AI systems more scalable, efficient, and accessible. We currently have internship openings in our Engineering Team for MSc students in Dortmund - North Rhine-Westphalia - Germany and the surrounding area, offering a 6-month term with the possibility of extension, in the following areas: Your ResponsibilitiesDepending on your area of expertise, you will support one or more of our engineering teams in the following areas:Digital DesignSupport the RTL design of digital circuits using SystemVerilog or VHDL.Contribute to the development, analysis, and optimization of digital logic.Support synthesis flows and evaluate synthesis results.Digital VerificationDevelop and maintain verification environments using SystemVerilog and UVM.Create and execute functional tests.Support the implementation of SystemVerilog Assertions.Physical DesignSupport floorplanning, place-and-route, and design implementation activities.Contribute to Static Timing Analysis tasks.Develop automation and data-analysis scripts.Analog DesignSupport the development and analysis of analog and mixed-signal circuits.Contribute to SPICE-based circuit simulations.Support high-speed SerDes, PLL, or related connectivity design activities.Your QualificationsCurrently enrolled in a Master's degree program in Dortmund- North Rhine-Westphalia-Germany and the surrounding area in Electrical Engineering, Microelectronics, Telecommunications Engineering, Information Technology, Computer Engineering, or a related field, with a completed Bachelor's degree.Basic knowledge in at least one of: digital design & RTL, digital verification, physical design, or analog/mixed-signal design.Structured, analytical, and detail-oriented working style with clear documentation skills.Preferred Additional SkillsDepending on your area of assignment, the following are a plus:Digital: SystemVerilog, VHDL, UVM, SystemVerilog Assertions, or formal verification.Physical Design: Static Timing Analysis, CDC analysis, floorplanning/place-and-route, Cadence Innovus or Synopsys ICC2.Analog: SPICE simulation, Cadence Virtuoso, high-speed SerDes or PLL design.General: Python, Tcl, or Perl scripting; version-control systems and automated development flows.What We OfferHands-on exposure to real semiconductor and connectivity projects, working closely with experienced engineering teams.The chance to apply your Master's coursework to real-world engineering tasks in an international environment.Flexible working hours with meaningful, independent responsibilities and hybrid options where applicable.ApplicationPlease submit your CV and include the following information:Your Master's degree program, university, and expected graduation date.Proof of current enrollment.Preferred technical area of assignment and availability (hours per week).Relevant experience (projects, internships, EDA tools/languages) and earliest possible start date.Find Jobs in Germany on Arbeitnow